1. Field of the Invention
The present invention relates to a digital transfer system, and more particularly to an apparatus for and a method of generating .pi./n-shifted n-differential encoded phase shift keying modulation signals which are used to modulate a serial string of binary data into a .pi./n-shifted signal.
2. Description of the Related Art
In digital communication systems, a digital signal is converted into a signal of a desired frequency band in accordance with a modulation method in order to carry out transfer of the digital signal. Such a modulation method used in digital communication systems includes an amplitude shift keying (ASK) method, wherein the amplitude of a carrier wave is modulated by a digital signal, a frequency shift keying (FSK) method, wherein the frequency of a carrier wave is modulated by a digital signal, and a phase shift keying (PSK) method, wherein the phase of a carrier wave is modulated by a digital signal. Among these modulation methods, the PSK method is the representative method for digital communication systems.
For example, in a digital communication system such as a cellular phone, a digital signal is modulated for its transfer in accordance with a .pi./4-shifted DPSK (differential phase shift keying) method. Developments in communication technology have resulted in a requirement for the transfer of data in an increased quantity. Due to such a requirement, the quantity of digital signals to be modulated inevitably increases. Under this condition, an apparatus for generating a .pi./16-shifted 16-DPSK modulation signal has been proposed.
FIG. 1 is a block diagram illustrating a conventional apparatus for generating a .pi./16-shifted 16-DPSK modulation signal. As shown in FIG. 1, the apparatus includes a serial-to-parallel converter 102 adapted to convert an input binary data stream, bm, into four parallel data streams Xk, Yk, Zk and Ak. The input binary data stream, bm, is a serial data stream. By the serial-to-parallel converter 102, consecutive first, second, third and fourth bits of the input binary data stream, bm, are converted into 1-bit parallel streams Xk, Yk, Zk and Ak, respectively. That is, the serial-to-parallel converter 102 outputs a 4-bit parallel data combination. A differential phase encoder 104 is also provided which receives the 4-bit parallel data combination from the serial-to-parallel converter 102. Based on the received 4-bit parallel data combination, the differential phase encoder 104 determines a variation in phase, .DELTA..phi.. The differential phase encoder 104 generates .pi./16-shifted 16-DPSK modulation signals Ik and Qk, based on the determined phase variation. The determination of the phase variation by the differential phase encoder 104 is carried out in accordance with a rule shown in the following Table 1. The generation of the .pi./16-shifted 16-DPSK modulation signals Ik and Qk is carried out in accordance with the following Equation 1.
TABLE 1 ______________________________________ Relation Between Input Data and Variation in Phase in /16-Shifted 16-DPSK Xk Yk Zk Ak .DELTA..phi. ______________________________________ 0 0 0 0 /16 0 0 0 1 3/16 0 0 1 0 5/16 0 0 1 1 7/16 0 1 0 0 9/16 0 1 0 1 11/16 0 1 1 0 13/16 0 1 1 1 15/16 1 0 0 0 -15/16 1 0 0 1 -13/16 1 0 1 0 -11/16 1 0 1 1 -9/16 1 1 0 0 -7/16 1 1 0 1 -5/16 1 1 1 0 -3/16 1 1 1 1 -/16 ______________________________________
As shown in Table 1, a variation in phase, .DELTA..phi., is determined in accordance with a parallel data combination of 4 bits, namely, Xk, Yk, Zk and Ak. In Table 1, each parallel data combination of 4 bits, Xk, Yk, Zk and Ak, is shown as a combination of binary codes, for the convenience of explanation. Instead of such binary codes, however, gray codes exhibiting a high resistance to noise may be used for the parallel data combination. EQU Ik=Ik-1.multidot.cos [.DELTA..phi.(Xk,Yk,Zk,Ak)]-Qk-1.multidot.sin [.DELTA..phi.(Xk,Yk,Zk,Ak)] EQU Qk=Ik-1.multidot.sin [.DELTA..phi.(Xk,Yk,Zk,Ak)]+Qk-1.multidot.cos [.DELTA..phi.(Xk,Yk,Zk,Ak)] (1)
In the above Equation (1), Ik is a current in-phase component modulation signal, whereas Qk is a current quadrature-phase component modulation signal. In addition, Ik-1 and Qk-1 are in-phase and quadrature-phase component modulation signals from the previous pulse interval, respectively.
As mentioned above, the conventional .pi./16-shifted 16-DPSK modulation signal generating apparatus converts a serial binary data stream into 4-bit parallel data combinations, thereby deriving a variation in phase. Using the derived phase variation, the apparatus generates an in-phase component modulation signal Ik and a quadrature-phase component modulation signal Qk. In order to derive the in-phase and quadrature-phase component modulation signals Ik and Qk, a calculation using Equation (1) is executed. In other words, it is necessary to carry out calculations such as sine function, cosine function, multiplication, addition and subtraction. However, it is difficult to practically configure hardware for processing such calculations. Although hardware for the calculation of Equation (1) may be configured, its configuration is considerably complex. Where the calculation of Equation (1) is processed using software, there is a problem in that a considerably lengthy computation time is required for the processing.